Principal PLL Design Engineer
- Employment type
- Full-time · On-site
- Posted
- November 10, 2026
- Province
- Ontario (ON)
Hiring confidence: Sparse posting · 22/100
This posting is missing most of the signals we look for, or shows patterns common to listings that are not actively being filled. Check with the employer before applying. How this is scored
Job Overview
This role is based in Ontario. Celero Communications is hiring for this full-time position through Jobily, where you can check how well your resume matches the posting before you apply.
Market context
About this role in Ontario
Average salary for Principal PLL Design Engineer in Ontario
We do not have a salary benchmark for this title in Ontario yet. The posting does not state a salary either.
NOC code
This posting has not been matched to a NOC 2021 unit group yet. Use the NOC finder to identify the code from the duties listed above.
Typical qualifications for Canadian employers
- Expertise in PLL design and high-speed CMOS analog circuits
- Experience with clocking circuits for optical transceivers
- Knowledge of high-speed SerDes systems
- Experience with ADC/DAC system design
- Strong background in analog and mixed-signal IC design
Fit check
Is this role right for you?
Top skills this posting asks for:
- PLL Design
- High-Speed CMOS
- Analog Design
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What you'll do
- Design and architect PLL circuits for next-generation AI systems
- Develop clocking solutions for optical transceivers
- Design high-speed SerDes clocking systems
- Create clock circuits for ADC/DAC systems
- Deliver disruptive high-speed interconnect technology
- Lead technical initiatives in a fast-growing startup environment
What you'll need
- Expertise in PLL design and high-speed CMOS analog circuits
- Experience with clocking circuits for optical transceivers
- Knowledge of high-speed SerDes systems
- Experience with ADC/DAC system design
- Strong background in analog and mixed-signal IC design