Principal PLL Design Engineer
- Employment type
- Full-time · On-site
- Posted
- September 29, 2026
- Province
- Ontario (ON)
Hiring confidence: Sparse posting · 7/100
This posting is missing most of the signals we look for, or shows patterns common to listings that are not actively being filled. Check with the employer before applying. How this is scored
Job Overview
This role is based in Ontario. Celero Communications is hiring for this full-time position through Jobily, where you can check how well your resume matches the posting before you apply.
Market context
About this role in Ontario
Average salary for Principal PLL Design Engineer in Ontario
We do not have a salary benchmark for this title in Ontario yet. The posting does not state a salary either.
NOC code
This posting has not been matched to a NOC 2021 unit group yet. Use the NOC finder to identify the code from the duties listed above.
Typical qualifications for Canadian employers
- PLL design expertise
- High-Speed CMOS analog design experience
- Experience with clocking circuits
- Knowledge of optical transceivers or high-speed SerDes
- Understanding of ADC/DAC systems
Fit check
Is this role right for you?
Top skills this posting asks for:
- PLL Design
- High-Speed CMOS
- Analog Design
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What you'll do
- Design high-speed CMOS PLL circuits
- Develop clocking solutions for next generation optical transceivers
- Architect solutions for high-speed SerDes systems
- Design PLL circuits for ADC/DAC applications
- Deliver disruptive high-speed interconnect technology for AI applications
What you'll need
- PLL design expertise
- High-Speed CMOS analog design experience
- Experience with clocking circuits
- Knowledge of optical transceivers or high-speed SerDes
- Understanding of ADC/DAC systems